You will be in charge of the development, maintenance, and verification of multiple designs. In this role, you will:
• Be in charge of the design of one or more digital hardware modules
• Take responsibility for the verification of one or more modules
• Investigate new technologies and techniques for AI acceleration
• Help and supervise less experienced colleagues
• Our expectation for junior engineers is to quickly become a reference point for younger colleagues, preparing themselves for a senior engineer position.

Profile

Committed to making your colleagues and team successful, you’re a good communicator willing to support younger team members. You’re curious, solutions orientated and a problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome and then to improve it once more.

You have:
• Knowledge of digital circuit design techniques and methodologies
• Knowledge of SystemVerilog, Verilog or VHDL
• Experience of FPGA/ASIC design or... verification

You might also have some knowledge or understanding of:
• Deep Learning and Artificial Intelligence
• UVM (or similar digital verification methodology)
• Low power design techniques and power-aware verification
• Object-Oriented Programming (OOP)
• Python

Tagged as: python, verilog, systemverilog, object-oriented programming, vdhl
Switzerland

Salary Criteria