Job Description

and

Requirements We're looking for a Senior Analog Design Engineer to join our team.

Does this sound like a good role for you?

In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP.

You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET process nodes. Working from Ser Des standards to block specifications, you quickly identify potential circuit architectures and successful design strategies.

You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Job Responsibilities Review Ser Des standards to develop analog sub-block specifications.

Identify and refine circuit architectures to achieve optimal power, area and... performance targets.

Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.

Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.

Present simulation data for peer and customer review.

Document design features and test plans.

Consult on the electrical characterization of your circuit within the Ser Des IP product. Propose solutions for post-silicon design updates.

Job

Requirements

PhD with 1 years, or MSc with 3 years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of depth familiarity with transistor level circuit design - sound CMOS design fundamentals.

Detailed design experience with one, and familiarity with several other Ser Des sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DACAware of ESD issues (i.e. circuit techniques, layout).Familiarity with custom digital design (i.e. high-speed logic paths).Knowledge of design for reliability (i.e. EM, IR, aging, etc.).Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).

Experience with tools for schematic entry, physical layout, and design verification.

Hands-on experience with physical layout of high-speed circuits is a plus.

Knowledge of SPICE simulators and simulation methods.

Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.

Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.

Good communication and documentation skills

The base salary range across the U.S. for this role is between $97,000 to $169,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.

Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Category Engineering Country Italy Job Subcategory Analog Design Hire Type Employee

Requisition Number: 42986

BRHiring

Location:

ITALY - Italy, ITALY - Pavia
Pavia Province of Pavia Italy

Salary Criteria