Job Responsibilities: Involved into simulation and verification tasks of SOC / IP designs Working with design teams for design function verification & performance evaluation Reusable verification environment development, methodology research & flow setup Supporting design debug , FPGA emulation , lab validation, silicon bring up and mass production ,etc Period: Permanent Working Hours: Office hours (Monday to Friday, 9-6pm) Salary: $7,000 - $14,000 Location: Ubi Requirements: BS/MS in Electronic/communication/automation engineering or related major. Experienced with System Verilog , C/C++ , tcl/python/perl. Solid project experience of SOC / IP designs : have taken responsibility for verification of SOC top/sys/ip/bus(CPU,DSP,GPU,DMA,AMBA,PCIE , MIPI , DDR, USB, UFS, etc) Experience with EDA tools : VCS / Verdi / Modelsim or similar tool sets. Experience with verification methodology (UVM,etc). Hands on verification platform / flow setup is a plus. Familiar with SOC design flow... Knowledge with low power design verification, familiar with UPF / SDC is a plus. Experience or knowledge with simulation accelerate flow / platform (Palladium/ZEBU). Self Motivated and fast learner. Interested applicants, kindly email your detailed resume (MS Word format is preferred): [HIDDEN TEXT] (Registration no: R2092012 ) Please ensure that applications sent through email are no bigger than 1Mb. We thank all applicants for your interest but regret to inform that only shortlisted candidates would be notified. Success Human Resource Centre Pte Ltd (EA License Number: 97C4832) 3 Shenton Way, 19-01 Shenton House, Singapore 068805 T: 6337 3183 | F: 6337 0329 | W: www.successhrc.com.sg Skills: Documentation Skills, Eda, Uvm, Ip, Fpga, Vcs, Human Resource, systemverilog, Ethernet, Flash, Functional Verification, Asic, Verilog, silicon, Vlsi Experience: 5.00-7.00 Years
Singapore

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