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Position: Design Verification Engineer...

Location: Remote

Duration: Long Term

Responsibilities:
• Understand the standards/specifications
• Project Planning, Scheduling and tracking
• Architecture development and documenting implementation level details
• Hands on work for every aspect of verification cycle
• Developing and delivering Verification IPs
• Responsible for the compliance with the latest Methodologies.
• Define Functional Coverage matrix and Comprehensive Test plan
• Regression management and functional coverage closure
• IP delivery sign-off

Required Skills:
• Project Planning, management and reporting experience
• Hands-on experience of complete verification cycle with strong verification concepts
• Strong knowledge of Verilog, SystemVerilog and UVM
• Experience in UVM based Verification IP development process lifecycle
• Experience in AMBA AXI/AHB/APB System buses
• Hands on work experience on any of PCIe/Eth/USB/DDR etc.
• Hands on experience with System Verilog Assertions
• Scripting for automation, release process, simulations, regressions
• Good command over written and oral communication

Contact Details:

Nitesh Kumar
• provided by Dice
United States

Salary Criteria