jobs description

Annapurna Labs builds high-performance hardware and software solutions used in AWS data centers globally. We are seeking a Serdes/PCIE Phy expert with a role in the definition, design, and validation of AWS next-generation ML Chips, Cards, and server integration. As a senior member of our platform development team, you will have the outstanding and meaningful opportunity to participate in the design and execution of all Serdes/PCIE topics, with the goal of creating customized platforms that fit within AWS datacenter’s world-leading technology. The Serdes/PCIE PHY Expert will need to independently work with vendors, understand the settings, write/modify tests, debug, and collect data.

Key job responsibilities:

1. As a senior member of the team, you will join a group of hardworking engineers to design and implement innovative next-generation machine learning chips and servers. In this position, you will make a real impact in a dynamic, technology-focused team. Your work will impact the growing field of machine learning.
2. You will collaborate with architects, design teams, and software engineers to deliver the next generation ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design, bring up, characterization, and validation.

We are open to hiring candidates to work out of one of the following locations:

Austin, TX, USA | Cupertino, CA, USA

Minimum Qualifications:

1. BS or MS in EE, ECE, or CS
2. 7+ years of experience in Silicon development with 3+ years in SOC/IO/Subsystems
3. Deep understanding of Serdes/PCIE at the PHY and controller level including inner workings of PHY component blocks
4. Familiar with industry-standard protocols such as PCIE
5. Experience with test chip characterization and testing compliance
6. Experience with post-silicon testing including shmoos, BER, PRBS, and EQ settings
7. Drive the IP Integration and design of silicon and 2.5D packaging
8. Support the physical design team, review clocking and timing constraints
9. Drive cross-functional triage effort on complex functional and performance issues
10. Take the leadership role in post-silicon bring-up including test plans and execution
11. Knowledge of channel electrical and associated tuning parameters, e.g., TX PSET values, RX equalization
12. Perform system-level debug and root-cause analysis through bring-up, characterization, validation, and production phase
13. Experience working with 3rd party IP vendors
14. Strong firmware development skills within embedded environments

Additional Qualifications:

1. Good leadership skills and ability to multi-task and thrive in a dynamic environment
2. Knowledge of PCIE and related protocols
3. Good communication and interpersonal skills

Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit here .

Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $127,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit here . This position will remain posted until filled. Applicants should apply via our internal or external career site.

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Cupertino CA United States

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Apply - Serdes PHY Expert, Annapurna Labs