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jobs description

Job Summary:

A Principal Digital Verification Engineer will lead the development of the Digital Verification framework and infrastructure for complex digital and mixed-signal ICs using cutting-edge technologies and industry-standard ASIC tools. The products may include power management, signal management, and mixed signal functions.

MPS products consist of switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for rapidly growing portable and non-portable markets like notebooks, cell phones, telecom, digital cameras, automobiles, and network equipment.

Essential Functions:
• UVM and System Verilog based Digital Verification environment definition and development.
• VIPs standardization, definition, development, and documentation.
• Integration of VIPs into the Project's Digital Verification environment.
• Digital Verification Metrics definition for RTL and Gate-Level Verification.
• Test Plan definition and development.
• Digital... Verification Automation and Scripting.
• Regression infrastructure definition, development, and management.
• Collaboration with Senior Digital and Analog Designers to develop VIP models.
• Leadership of the Digital Verification Team.
• Supervision of Digital Verification Tasks for multiple projects.
• Review of Digital Verification Metrics and Results for multiple projects.
• Design of Digital Verification Top-Level Tests.
• Analysis and debugging of test results, code coverage, and functional coverage.
• Estimation, planning, and scheduling of Digital Verification activities to meet project deadlines.

• PhD/BS/MS in Electrical Engineering with focus on Digital Design/VLSI coursework.
• Over 10 years of experience in ASIC Verification.
• Experience in power management DC-DC converters and control topologies, such as PWM control, constant-on-time control, and voltage/current mode controls.
• Proficiency in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
• Proficiency in DV skills and areas like Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, and UVM DV Agents (Monitor, Driver, Scoreboard).
• Strong knowledge and experience across the entire Digital Design Flow.
• Expertise in industry standard ASIC tools/flow for daily work.
• Strong scripting and automation skills using TCL, Python, or C/C++.
• Leadership skills for guiding the DV Team and mentoring Junior DV Designers.
• Effective written and verbal communication skills and emphasis on teamwork and collaboration.
• Additional experience with automotive standards, embedded MCU designs, and communication protocols is a plus. Ability to communicate in Chinese is highly desirable.

• Barcelona, Spain
• Portugal (Lisbon/Porto)
• Netherlands (Enschede/Nijmegen)
• Switzerland (Tolochenaz
Barcelona Spain


Apply - Principal Digital Verification Engineer Barcelona