Job Description
Title/Position: SV/UVM Verification Engineer
Role: Full-time/Permanent
Location: EU/UK - Bristol, UK, or Munich, Germany.
Company Overview
Recmatrix Consulting's client is a Design and Test Engineering Service Company offering End-to-End Solutions encompassing Product Engineering, Software, Hardware, Wireless, Automotive, and Embedded Solutions. Candidates should possess strong problem-solving skills, attention to detail, and the ability to work effectively both independently and as part of a team. Excellent communication skills and a proactive approach to addressing challenges are also essential.
Key Responsibilities
• 5+ years of experience in Digital IP verification utilizing System Verilog/UVM methodologies.
• Develop testbenches for a non-volatile memory IP.
• Creation of agents to facilitate verification processes.
• Adapt existing tests and develop new tests for new features of the NVM IP.
• Demonstrate that the relevant tests are passing and meet the... specified criteria.
• Define verification coverage to ensure comprehensive testing.
• Qualify testbenches using Certitude.
• Document verification results for reference and future analysis.
• Provide evidence of passing relevant tests.
• Ensure verification coverage (both structural and functional) is achieved.
• Verify that the testbenches meet the required quality standards.
• Experience with TSMC processes is preferred
Cambridge UK