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ASIC DFT Synthesis Engineer - Paris Sequans Communications Paris

ASIC DFT Synthesis Engineer - Paris

2020-11-18 10:04:37
ASIC DFT Synthesis Engineer - Paris
In the BB IC team, you will be responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing) of part of Sequans’ next generation LTE IC. You will work closely with several teams: Software, Signal processing algorithms, integration and Layout.

Required Skills & Experience
• Engineering degree
• Minimum of 4 years experience of ASIC synthesis (including writing SDC), DFT (including scan and MBIST) and equivalence check, ideally with Cadence tools
• Good experience of Verilog/VHDL
• Knowledge of CPF and Cadence CLP would be a bonus
PROFILE
• Fast learning capabilities, highly motivated, self-starter, autonomous
• Ability to work in a fast moving and multicultural environment
• Team player, commitment & customer focus
• Excellent written and oral communications skills, fluent English
Paris France
ASIC DFT Synthesis Engineer - Paris Sequans Communications Paris
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